1. Field of the Invention
The present invention relates to a technology that enables consideration of an early pin assignment by using a package-designing CAD apparatus in designing a printed circuit board including an integrated circuit such as a Programmable Logic Device (PLD) component and a technology for supporting (aiding) designing a circuit in which an integrated circuit for a PLD or the like is used as a component.
2. Description of the Related Art
In designing a printed circuit board including a PLD component such as Field Programmable Gate Array (FPGA), a PLD designer, a circuit designer, and a package designer exchange design information such as pin assignment information.
A PLD-designing CAD apparatus for supporting PLD designing, a circuit-designing CAD apparatus for supporting circuit designing, and a package-designing CAD apparatus for supporting package designing respectively hold design information, and thus it is important to maintain a consistency among the design information held by each of the apparatuses. Therefore, for example, when pin assignment is changed in package designing, the change needs to be reflected in PLD design information.
Consequently, a technology has been developed in which pin replacement in package designing is reflected in PLD design information. For example, Japanese Patent Application Laid-Open No. 2006-79447 discloses an FPGA design supporting apparatus in which information on changed pin layout can be reflected in FPGA design information.
However, there is a problem that a component shape type library is required to consider a package design by using the package-designing CAD apparatus, though, there is no component shape type library of the PLD component when the PLD designer and the package designer consider an early pin assignment. Therefore, the package designer cannot consider the pin assignment by using the package-designing CAD apparatus.
Furthermore, a conventional circuit-designing CAD apparatus performs a design rule check of a circuit diagram, which is designed by a circuit designer, by referring to a component library. In this case, as the design rule check, there are described, for example, an input/output attribute check to check whether the number of output pins is one by using an input/output attribute of each of pins with respect to each of nets, a differential signal check to check whether all pins included in a net have the same differential attribute, and a power-supply voltage check to check whether a voltage value of a power supply pin is identical to a power supply voltage of a net.
Moreover, Japanese Patent Application Laid-Open No. H4-246778 discloses such a technology that, when input/output pins of a semiconductor integrated circuit are to be arranged, the input/output pins are arranged after being subjected to a physical check and an electrical check by using logical connection information, package information, and library information.
However, when a circuit-design supporting apparatus performs a design rule check of a circuit diagram in which a PLD such as an FPGA (Field Programmable Gate Array) is used as a component, precise information on the PLD is not registered in a component library to be referred by the circuit-design supporting apparatus. Therefore, the design rule check cannot be performed precisely.
Namely, in the component library, a pin attribute (an input/output attribute, a differential attribute, a power supply voltage, and the like) of the PLD is not an attribute that is obtained after a program is written. Therefore, it is not possible to perform the input/output attribute check, the differential signal check, and the power-supply voltage check.